Hierarchical modeling for VLSI circuit testing / by Debashis Bhattacharya and John P. Hayes.

By:

Contributor(s):

Publication details: Boston : Kluwer Academic Publishers, 1990Description: 159 p. : ill. ; 23 cmISBN:

Subject(s):

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Home library	Collection	Call number	Materials specified	Copy number	Status	Date due	Barcode
AM	PERPUSTAKAAN LINGKUNGAN KEDUA	PERPUSTAKAAN LINGKUNGAN KEDUA KOLEKSI AM-P. LINGKUNGAN KEDUA	-	TK7874.B484 (Browse shelf(Opens below))		1	Available		00000815202

There are no comments on this title.

to post a comment.