Bhattacharya, Debashis,  1961- <br/><br/>
Hierarchical modeling for VLSI circuit testing / 
by Debashis Bhattacharya and John P. Hayes. 
 - Boston :  Kluwer Academic Publishers,  1990 
 - 159 p. :  ill. ;  23 cm. 
<br/><br/><label>ISBN: </label>079239058X  RM203.11 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Testing.<br/>Integrated circuits--Very large scale integration--Computer simulation.