TY  - BOOK
AU  - Bellido,Manuel J.
AU  - Juan Chico,Jorge
AU  - Valencia,Manuel
TI  - Logic-timing simulation and the degradation delay model
SN  - 1860945899 (hb)
AV  - TK7868.T5 B385
PY  - 2006///
CY  - London
PB  - Imperial College Press
KW  - Timing circuits
KW  - Integrated circuits
KW  - Very large scale integration
KW  - Metal oxide semiconductors, Complementary
N1  - Includes bibliographical references
UR  - http://www.loc.gov/catdir/toc/fy0705/2007271541.html
ER  -