Bellido, Manuel J.,  1964- <br/><br/>
Logic-timing simulation and the degradation delay model / 
Manuel J. Bellido, Jorge Juan, Manuel Valencia 
 - London :  Imperial College Press,  2006 
 - xvii, 267 p. :  ill. ;  24 cm. 
<br/><br/>Includes bibliographical references 
<br/><br/><label>ISBN: </label>1860945899 (hb)  RM147.42 9781860945892 (hb) 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Timing circuits<br/>Integrated circuits--Very large scale integration<br/>Metal oxide semiconductors, Complementary
<br/><br/><label>LC Class. No.: </label>TK7868.T5  / B385